An ASIC Design Engineer helps the verification team and undertakes various duties such as – developing digital components, integrating and testing software, delivering ASIC designs in due time, and performing electrical analysis. Other related duties are listed on the Asic Design Engineer Resume as – identifying micro-architectural performance bottleneck in load/store units; creating the framework, workloads for running JavaScript benchmarks; identifying and exploring new researches in computer architecture, writing and debugging VERA test benches and tests, and debugging of high-speed switch fabric ASIC.
Those interested in this role must emphasize in their resumes the following skills – digital circuits knowledge and expertise, analytical thinking skills, time management skills, project management skills, the ability to utilize the latest technologies, and problem-solving attitude. Successful candidates for this role often hold a degree in fields such as Computer Science or IT.
Objective : As an Asic Design Engineer, responsible for the development of FPGA/ASIC devices. The individual will take a lead role in developing leading-edge digital imaging products for a pre-IPO company.
Skills : Oscilloscopes, Function Generators, Multi-meters, Spectrometers.
Description :
Worked both as an individual contributor and as a project lead to perform ASIC and FPGA-based design.
Mapped complex DSP and digital coding algorithms into synthesizable VHDL and Verilog.
Performed synthesis using Synopsys, Primetime, Synplicity, Xilinx ISE, Altera Quartus design tools.
Responsible for top-level Synopsys synthesis scripts, as well as and sub-module scripts.
Performed simulation using, ModelSim, Aldec, Cadence, and a variety of other simulators.
Prototyped ASICs on Xilinx, Altera, and Actel FPGAs.
Verified and validated all designs.
Experience
2-5 Years
Level
Junior
Education
MS
Asic Design Engineer Resume
Objective : Seeking an ASIC Design Engineer position, responsible for the Leading position in the development of FPGA based digital devices using synthesis techniques, and also Working with the systems team to architect and develop leading-edge digital imaging products.
Led position in the development of FPGA based digital devices using synthesis techniques.
Worked with the systems team to architect and develop leading-edge digital imaging products.
Developed block diagrams, product development plans, and required documentation.
Ran and debugged tests for product development and the integration device into the final product.
Experienced designing with various network protocols in FPGAs, ideally with experience in low latency optimization.
Experienced with system-on-chip (SOC) architectures, memory & processor subsystems, and peripheral interconnect.
Designed key processing blocks of GEOs next-generation camera processors.
Experience
2-5 Years
Level
Executive
Education
BS
Asic Design Engineer Resume
Headline : As an Asic Design Engineer, responsible for Collaborating with the verification team to develop block-level verification test benches & tests, and also Working with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks.
Worked closely with three engineers on Servo digital block in Read-Channel chips including the first 28-nm read-channel chip in the industry.
Designed Servo block output module, error injection module, and TestMux module in SystemVerilog and doubled date processing performance under new chip system structures.
Designed and implemented a brand new Viterbi algorithm module in SystemVerilog in a new chip to increase decoding accuracy in high-volume and high-speed data from 0.2 to 0.7 dB depending on CBDs.
Created block-level test bench and test cases, and verified design blocks by SimVision and Verdi.
Established directed and constrained random test cases to perform simulations based on OVM/UVM.
Implemented gate-level ECO by formality.
Mentored new hires to familiarize them with the working environment and basic products.
Experience
5-7 Years
Level
Executive
Education
BS
Asic Design Engineer Resume
Objective : As an Asic Design Engineer, responsible for using QuestaSim, Xilinx Vivado, Xilinx FPGAs, and Synopsys timing constraints or equivalent, working on multiple projects in parallel and effectively document designs and communicate with co-workers.
Skills : ASIC Physical Design, RTL To GDSII, Communication.
Description :
Worked on the 40G (OC768) system project.
Responsible for designing an ATM interface for the Chip.
Designed FIFO controllers for data handoff between different clock domains.
Designed all the blocs for the internal self-integrity data checks functionality.
Participated in the design of our very complex FEC encoder.
Designed was about 2M gates excluding memories and macros.
Responsible for simulating many blocs at the top level (FEC, ATM, EBUS, ).
Experience
2-5 Years
Level
Junior
Education
MS
Asic Design Engineer Resume
Objective : Highly qualified Asic Design Engineer with experience in the industry. Enjoy creative problem solving and getting exposure on multiple projects, and I would excel in the collaborative environment on which your company prides itself.
Responsible for the power analysis of the Chip using sequence' Power analysis toolset.
Designed and verification of components used in DO-254 Level A fly-by-wire actuator controllers.
Developed a specification of the processor micro-architecture
RTL implemented key building blocks of the processor
Analyzed performance and make implementation choices to optimize timing
Analyzed and optimized the design for power efficiency and power integrity
Worked with verification and physical design teams to achieve a high-quality design and successful tapeout.
Experience
2-5 Years
Level
Junior
Education
GED
Asic Design Engineer Resume
Headline : A top producer in Asic Design Engineer with the ability to deliver high-quality designs and meet aggressive deadlines, with extensive experience in computer engineering design and implementation, specializing in logic design and verification in the areas of IP integration in SoC, and Flash memory Host Controller IPs. Has demonstrated the ability to quickly and easily master new programming languages, tools, designs, and architectures. Key strengths include creativity, problem-solving, attention to detail, and envisioning new concepts.
Designed and verified both master and slave interfaces in compliance with the standard 200MHz QDR bus protocol for use in a Network processor to CAM (content addressable memory) interface chip.
Designed and verified the DDR command interface and the DDR result/cascade interface of a CAM ASIC.
Created a behavioral model of the CAM memory core.
Resulted in 100% functionality in the first silicon and IP patents.
Designed, simulated, and synthesized the host interface of an Ethernet switch system on a chip.
Integrated a PCI Core, and assisted in the designing of the Reassembly Controller Packet Editing function to keep on schedule.
Integrated and verified a TV Output Logic Core and a Video Input Core in a 3D graphics chip, and redesigned the Flicker Filter Unit to the reduced logic area.
Experience
5-7 Years
Level
Executive
Education
MS In Computer Engineering
Asic Design Engineer Resume
Objective : ASIC Design Engineer with 2+ years of experience in ASIC physical designing and NAND flash memory design with more than one year of Quality Engineering and Assurance debugging experience, physical design internship, and coursework.
Designed FPGAs and ASICs for a Terabit core router.
Performed 1st pass synthesis (Fujitsu 0.18um CMOS process), timing analysis as well as targeted tests for DV and lead ASIC to bring up in lab, support module/software for system integration.
Performed module-level P&R using Silicon Ensemble/Primetime, achieved timing closure for 311MHz clock(Fujitsu 0.18um CMOS process).
Completed logic synthesis and gate-level simulation.
Resulted in a valuable IP when the company was sold.
Solved customer problems through innovative enhancements to product architecture/ micro-architecture.
Worked with the marketing and development team to refine product spec/methodology.
Experience
2-5 Years
Level
Executive
Education
G.E.D
Asic Design Engineer Resume
Summary : Over 15 years of experience in high-density Asic Design Engineer Gate Arrays (FPGA) and Programmable Logic Devices (PLD) design and verification. The total hardware design experience exceeds 20 years. Very strong practical knowledge of VHDL/Verilog design flow including synthesis, simulation, and verification.
Designed and implemented SSD Controller ASICs for flash interface subsystems.
Designed and implemented Programmable Sequencer based RTL for NAND flash protocol to handle up to 800MT/s bus speed ONFI, NV-DDR3 mode.
Understood of microcode for the Sequencer to execute Flash Commands.
Designed and implemented of NIST published FIPS 180-2 HMAC SHA-256 IP module for 8Mb/s RPMB access in the security subsystem for flash memory controller devices.
Verified the HMAC SHA-256 Security Subsystem IP using Verilog testbench based verification.
Performed timing analysis of flash protocol bandwidth consumption for latency in the Programmable Sequencer based Subsystem.
Debugged top-level simulation errors using spyglass reports.
Experience
10+ Years
Level
Senior
Education
MS
Asic Design Engineer Resume
Objective : A forward-thinking and driven ASIC Design Engineer, with extensive experience in all aspects of digital and processor system development, including architecture development, design, verification debug, and testing. Completes detailed critical analysis of business requirements to provide out-of-the-box solutions that add value to client systems.
Skills : Designing, Developing, Problem Solving.
Description :
Served as a customer technical interface for ASIC.
Contributed to the creation and revision of quality standards, communicating the impact of requirements change requests on subsystem design schedule, and communicating resources to customers and internal managers.
Developed and provided customer training on how to complete ASIC and 54x DSP designs.
Executed quality checks on customer handoffs during the design process, coordinating with the physical design team and validating converting test vector package.
Designed DSPs for customer ASICs.
Implemented multiple high-volume ASIC devices.
Achieved honor as a member of the group technical staff.
Experience
2-5 Years
Level
Executive
Education
MS In Electrical Engineering
Asic Design Engineer Resume
Summary : Over nine years of experience in hardware design and verification with a focus on ASIC, FPGA, SOC, and embedded systems with hardware and software interfaces. Consulted for Clients like Cisco, Cypress, Xingtera, Marvell, Samplify, Koolchip, Mindspeed, Ngcodec, MSTP, and Atria-logic. Extensive knowledge and design experience in PCIe, USB, Ethernet, AMBA, Avalon bus architecture.
Skills : System Engineering, Design Engineering, Interpersonal SKills.
Description :
SSD Device Controller SOC Responsible for various IP development and integration into SSD controller SOC.
Experienced 4 tape-out at 40nm technology.
Performed Gate-level simulations using Synopsys VCS and synthesis using Synopsys Design Compiler.
Performed Static timing analysis and generated a netlist file using the Design compiler.
Developed block/system level RTL to meet physical, DFT, and power goals.
Collaborated with the verification team to develop block-level verification test benches & tests.
Worked with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks.
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