The main job of a Component Design Engineer is to undertake responsibility for chip layout, circuit design, device evaluation, validation, and circuit checking. The most common work activities are listed on the Component Design Engineer Resume as – planning design projects, addressing the unique needs of the customers, ensuring specific parts used in manufactured products are reliable and effective, helping in designing new parts for larger systems or products; improving efficiency and effectiveness, taking responsibility for testing or installing pre-existing components, machinery, and equipment; participating in the design and testing of components, and providing technical consulting services.
Those seeking this job role must mention on the resume the following skills – basic understanding of manufacturing mechanical and electrical systems within the industry, experience in reading schematics for circuit designs, experience in specific computer programs such as Agile Software. A degree or an engineering degree is commonplace among job applicants.
Headline : Component Design Engineer with significant experience in hardware validation, ASIC verification and UEFI BIOS programming. Skilled in co-simulation hardware and software, using Verilog and System Verilog models. In-depth knowledge of logic design concepts and debug tools such as ITP and JTAG.
Skills : C, MATLAB, Perl.
Description :
Responsible for pre-silicon RTL validation for Intel Southbridge chipset and embedded/BIOS development for post-silicon verification.
Developed test pattern with Perl and performed RTL and DFT validation for Intel Southbridge ICH6 and ICH8 chipset on SATA and PCI-e interface.
Verified DMI RTL for ICH8 chipset and developed Arden and SATA test on fCPV for ICH8.
Involved in every aspect of 3GIO/PCI-e interface validation and device characterization on motherboard level with built-in DV for ICH6.
Tested application and algorithm were developed in .NET language.
Brought up the receiver eye width test script with additional functions so that different CMM values and random CMM values can be used when running the script to collect data.
Enabled the eye width and bit error rate to be checked whether they are affected by the different CMM data instead of the default CMM value.
Experience
5-7 Years
Level
Junior
Education
B.Eng In Electronics Engineering
Component Design Engineer Resume
Objective : Highly skilled with 4 years of experience in chip verification/validation, test plan development, scripting, regression, verification and debugging knowledge to Intel. Accomplished in acquiring skills in lab environment to resolving complex problems. Excellent communicator and team player as well as efficient independent worker.
Skills : Video Editing, Video Production.
Description :
Developed validation Test Plan for XHCI.
Found and debugged bugs in USB IP in the post-silicon environment on Intel-powered client SoC in C++ Pre-validation for USB IP was implemented in the FPGA environment for the future SoCs.
Validated power management features in USB IP to find if our driver is stable and ready for various SoC in C++ Worked on Physical layer failure which could have delayed in the health check of the USB IP during the post silicon validation with successfully colabarating with RTL designers, Architects.
Debugged OEM failures in USB IP for various client platform in system validation operating system in Windows and Linux environment Projects Ethernet packet loopback design verification using SystemVerilog o Description Design checks the incoming Ethernet packets at the receive interface for CRC, sof errors, data len errors, etc.
Developed basic scenarios targeting all features of AXI protocol.
Accurated modeling of these analog circuits was one of the main parts of the job.
Modeled captured scalability in length and width, full GM and GDS fitting including scalability and temperature scalability among other requirements.
Experience
2-5 Years
Level
Executive
Education
Master of Science
Component Design Engineer Resume
Objective : A highly energetic and motivated professional with excellent communication and interpersonal skills. As a quick learner with a continuous desire to adopt new skills, I am a dedicated team player who works well under pressure in a fast-paced environment. What sets me apart is my strong cross-cultural uidity and inherent value of diversity. I not only bring fresh perspective to problems, but my ability to patiently empathize and relate to people of all stripes makes me a unifying team force.
Successfully worked across multiple time zones with engineering teams in Folsom, Costa Rica, and Israel to enable the smooth ow of content from the test writing teams to the Fault Grade execution team.
Brainstormed and implemented an enhancement to the Check_In_Ivb.pl script to handle xed test turn- ins more e ciently.
Utilized the cross coverage tool to improve IMPH and MC coverage.
Ran several tests many of which were turned in with updated fubs giving more faults covered.
Took initiative to write two Perl scripts that parsed register names from an XML le and generated the associated .e test le.
Owned the FC CPUID regression.
Ramped on the test infrastructure, ran regressions and debugged failures.
Experience
2-5 Years
Level
Junior
Education
GED
Component Design Engineer Resume
Objective : To obtain a full-time Component Design Engineer position as a software engineer, network administrator, or database administrator in the Hampton Roads Area of Virginia, respectively.
Skills : C/C++, SQL, Shell Script, Perl, SQL Server 2005, Linux, Windows, VMware, VNC Server, MS Visual Studio, JDBC.
Description :
Executed industry-standard benchmarks in order to retrieve and interpret performance metrics and data using LeCroy Analyzer.
Presented analysis of benchmark data.
Provided suggestions to improve the first generation acceleration component based on the analysis of data.
Calibrated the tool utilized for benchmarking according to the benchmark specifications.
Created a back to back network between two servers in order to control the flow of traffic in a stress test of the system.
Captured the distribution of the system resources during the stress test, which allowed one to identify and eliminate processes that were consuming desirable resources.
Identified, installed, and tuned the proper Bios and OS in order to provide optimal performance and functionality.
Experience
2-5 Years
Level
Executive
Education
Master's of Engineering
Component Design Engineer Resume
Summary : Seeking a Device Engineer, Process Development Engineer, Device Modeling and/or Characterization Engineer position at semiconductor or related industry. EMPLOYABILITY Naturalized US citizen and immediately available to work.
Worked in TCAD and Compact Device Modeling Groups on device characterization, SPICE model generation, and debugging process integration issues and circuit-related issues.
Worked closely with Technology Development Group, Device Modeling Group, and Circuit Designers to define device performance and limitations, characterized DC and AC performance of devices, generated accurate compact models that debugged any circuit design issues related to device performance.
Modeled complex MOS devices for Flash control circuitry (Analog circuits), Flash cells, parasitic BJTs, Diodes, Capacitors, Resistors, and Interconnects.
Generated skew corners and did QA and FEM delay analyses.
Models had to be within strict fitting criteria imposed by the designers for different operating conditions.
Controlled Circuitry of flash memory was made of analog circuits.
These analog control circuits were required to perform read, write, and erase operations on the flash memory devices.
Experience
7-10 Years
Level
Management
Education
MSEE In Devices
Component Design Engineer Resume
Objective : Experienced RTL design engineer, with industry as well as academic experience of design, implementation, and complete lifecycle of highly complex digital modules like processors and controllers, self-driven and detail-oriented professional looking for a challenging position in RTL design that brings new opportunities to work on cutting edge products in mentally stimulating work culture.
Skills : Management Skills, DEsigning Skills, Communication Skills.
Description :
Designed, RTL implementation and debug of modules internal to XHCI controller, with features involving the design of components including Doorbell manager and synchronous FIFOs, etc for communication between Driver and Hardware, and communication between logic working on different clock domains and different Vdd.
Integrated of SubIPs into the XHCI and XDCI IP.
Flowed related activities like Synthesis using Synopsys DC, Lint, and other quality checks and runs, etc.
Tcl scripts for ECOs in legacy XHCI modules.
SystemRDL management for all Driver-visible XHCI and XDCI registers.
Designed, RTL implementation, and debug of XHCI internal memory space register file components.
Worked with different stake-holders and delivered multiple deliverables with acceptable quality and maturity, on time for multiple ongoing projects.
Experience
2-5 Years
Level
Executive
Education
M.S. In Electrical Engineering
Component Design Engineer Resume
Summary : Responsible for Debugging RTL simulations validating the functionality of new architectural features of next-generation designs by developing the validation test plan and participate in coverage analysis.
Skills : MS Office, Designing Skills, Engineering.
Description :
Randomized environment development and code randomization.
Created user accounts and groups to control access and privileges.
Collaborated with a team of architect engineers to capture requirements, identify microarchitecture (detailed design and logic), and completed code reviews for the second generation of an acceleration component using tools such as Live Meeting or Lync and conference calls.
Saved several man-months and surpassed schedule in completing verification by building an internal memory array checker scoreboard with an expected-value generator for formats in which the array read data would be returned.
Devised a cycle-accurate synthesis-compatible clock and reset filter in Verilog starting from timing diagrams; adopted for use in all future project simulations.
Experienced with spice simulators such as hospice, specter, etc.
Experienced with data management software such as DesignSync, Perforce, Git/Gatekeeper, etc
Experience
7-10 Years
Level
Executive
Education
MS
Component Design Engineer Resume
Objective : To find a Component Design Engineer position that will utilize my extensive experience in Hardware Physical Design, full-chip and local clock distribution, clock power reduction/estimation, and full-chip and block-level timing convergence.
Experienced in interface with engineers, managers, and other stakeholders by providing schedule updates and execution status.
Experienced with various Electronic Design Automation EDA software, PDK, flows, and architecture.
Experienced with Mentor Graphics Calibre DRC/LVS and Synopsys Star-RCXT is a plus.
Designed and promoted new components and sub-processes.
Performed needs analysis and initiate ideas.
Evaluated new products or processes.
Performed product maintenance.
Experience
2-5 Years
Level
Executive
Education
MS In Electrical Engineering
Component Design Engineer Resume
Headline : To find a Technical Lead position that will utilize my extensive experience in Hardware Physical Design, full-chip and local clock distribution, clock power reduction/estimation, and full-chip and block-level timing convergence.
Wrote core code blocks from scratch and supported Specman verification components, including JTAG, APIC, MCI, and LDAT, used on multiple generations of Knights many-integrated-core (MIC) processors.
Delivered code to synchronize Specman DFx sequences with processor opcode execution.
Collaborated with remote engineers to convert simulation tests to high-volume manufacturing testing hardware.
Created verification collateral for full-chip simulation environments.
Mentored employees learning the verification environment.
Ported test environments from previous processor projects to reuse.
Highlights Increased productivity by developing macros to reuse existing text stimulus input files as Specman e tests for the Specman TAP eVC with only minor formatting changes.
Experience
5-7 Years
Level
Executive
Education
MS In Electrical Engineering
Component Design Engineer Resume
Headline : Physical Verification: Strong knowledge in physical verification flows (DRC/LVS) and tape-in flow methodologies. Design Automation: Expertise in developing Makefile based automation for execution, data-mining, and report generation of ASIC physical design flow. Quality Assurance: Leading continuous improvement in DFM/Fill and DRC sunset quality through QA regression automation.
Skills : Designing Skills, Communication Skills, Developing Skills.
Description :
Developed and supported physical verification (DRC/LVS), tape-in utilities on leading advanced node technologies.
Developed and supported DFM/Fill flow sunsets, layout completion utilities, and documentation and release of the same in Process Design Kits (PDK).
Owned integration of DFM/Fill flows into design CAD tools viz.
Focused on PLL, clocking, IO, and thermal circuits as lead silicon debug engineer for several generations of x86 microprocessors from 0.25um to 65nm.
Debugged flow failures reported by customers and provide workaround/code-fixes in a timely manner.
Architected sequential flow execution and summary report generation of ASIC physical design flow starting from Synthesis to Physical Verification.
Designed QA regression infrastructure and QA tests for Process Design Kit (PDK) modules: DRC/LVS and DFM/Fill sunsets.
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