IC Design Engineer Resume Samples

Description :

1. Encouraged team members and partners to do the same.
2. Worked with architecture team to define micro-architecture for various design blocks & subsequently Verilog RTL development.
3. Developed system level tests using tcl, itcl, python, C/C++ and system verilog programming languages to verify networking switch chips and systems.
4. Worked knowledge of RF test equipment (network analyzer, spectrum analyzer, vector signal analyzer, vector signal generator).
5. Worked with digital designers to create behavioral models of analog blocks.
6. Established and implemented architectures and circuits of high-performance systems.
7. Validated circuit performance in the lab.

Experience

10+ Years

Level

Senior

Education

Bachelor's in EE

Description :

1. Worked with test engineers to validate analog designs.
2. Evaluated silicon performance.
3. Guided test plan development for production.
4. Performed development activities such as Synthesis, Formal Verification, and Static Timing Analysis.
5. Performed an End to End System performance analysis.
6. Worked closely together with colleagues from our production, design, and test engineering departments to produce high quality solutions.
7. Worked with architecture team to define DFT methodology for optimized fault coverage and test time.

Experience

7-10 Years

Level

Management

Education

Bachelor's in EE

Description :

1. Specified, architected and designed low voltage and low power RF/analog integrated circuits from product definition through characterization and qualification.
2. Provided guidance to layout designers and monitor progress of IC layout.
3. Developed and implemented test plans for lab characterization once design comes back from fab.
4. Experienced in designing mixed signal IO circuits including RX, TX, PLL, Bandgap bias.
5. Wrote constraints for layout synthesis.
6. Worked with test engineering and silicon debug.
7. Led with confidence – thought leaders who empower those around them.

Experience

5-7 Years

Level

Executive

Education

Bachelor's in CE

Description :

1. Responsible for developing RTL designs, synthesized logic gates, performed timing analysis, and implemented physical designs using VHDL/Verilog, Synopsys Design Compiler, and IC Compiler.
2. Responsible for conducting functional verification, simulation, and debugging of IC designs using simulation tools (ModelSim, VCS) and debugging techniques.
3. Responsible for collaborating with cross-functional teams, including architects, system engineers, layout designers, and test engineers, to define IC specifications, resolve design issues, and meet project milestones.
4. Responsible for participating in design reviews, design-for-testability (DFT) considerations, and design-for-manufacturability (DFM) optimizations to improve IC performance, yield, and reliability.
5. Responsible for assisting in post-silicon validation, testing, and characterization of ICs, analyzing performance metrics, signal integrity, and power consumption.
6. Responsible for designing and developing analog and mixed-signal circuits, including amplifiers, filters, oscillators, and data converters, for communication and signal processing applications.
7. Responsible for conducting circuit simulations, performance analysis, and design optimizations using SPICE simulators (HSPICE, LTspice) and circuit design tools.

Experience

2-5 Years

Level

Executive

Education

Bachelor's in CE

Description :

1. Experienced with ASIC/FPGA design flows, design constraints, timing closure, and design optimization techniques.
2. Collaborated with architects and system engineers to define IC specifications, design goals, performance targets, and project timelines.
3. Participated in project planning, feasibility studies, and technology evaluations to determine the best IC design approach and methodology.
4. Developed RTL (Register Transfer Level) designs using hardware description languages (VHDL, Verilog) to implement digital logic functions, circuits, and modules for ICs.
5. Synthesized RTL designs into gate-level netlists using synthesis tools (Synopsys Design Compiler, Cadence Genus) to optimize for area, power, and timing constraints.
6. Performed timing analysis, static timing closure, and clock domain crossing (CDC) analysis to meet timing requirements and achieve design robustness.
7. Provided engineering direction and judgment for developmental work in integrated circuit design, with due consideration for scientific and practical concerns.

Experience

2-5 Years

Level

Executive

Education

Bachelor's in EE

Description :

1. Developed and executed functional verification plans, testbenches, and verification environments (SystemVerilog, UVM) to verify IC functionality, performance, and compliance with specifications.
2. Conducted simulation, emulation, and formal verification techniques (ModelSim, VCS, Questa) to ensure correct behavior and functionality of IC designs.
3. Implemented design-for-testability (DFT) techniques, scan chains, built-in self-test (BIST) structures, and test access mechanisms (TAMs) to facilitate testability and production testing of ICs.
4. Collaborated with manufacturing and process engineers to optimize IC designs for manufacturability, yield improvement, process variability, and reliability considerations.
5. Addressed DFM issues such as lithography constraints, metal density rules, and design rules checks (DRC) during IC design and layout.
6. Collaborated with test engineers, validation engineers, and product engineers to debug issues, analyze test results, and resolve silicon validation issues.
7. Addressed physical design challenges such as congestion, timing closure, signal integrity, and power distribution during the physical design phase.

Experience

2-5 Years

Level

Executive

Education

Associate IC Design Engineer

Description :

1. Worked collaboratively with cross-functional teams, including architects, system engineers, layout designers, verification engineers, and manufacturing engineers, to achieve project goals and deliver high-quality IC designs.
2. Communicated progress, design status, issues, and recommendations to project stakeholders, management, and team members.
3. Expertised in digital and analog IC design methodologies, including RTL (Register Transfer Level) design, synthesis, physical design, verification, and testing.
4. Experienced in hardware description languages such as VHDL and Verilog for designing digital logic circuits, modules, and systems at the RTL level.
5. Experienced with EDA tools and software platforms used in IC design, including synthesis tools (Synopsys Design Compiler, Cadence Genus), physical design tools (IC Compiler, Innovus), simulation tools (ModelSim, VCS), and verification tools (UVM, Questa).
6. Wrote efficient and synthesizable RTL code adhering to design guidelines, coding standards, and design-for-synthesis considerations.
7. Experienced in developing verification plans, testbenches, and verification environments (SystemVerilog, UVM) for functional verification, simulation, emulation, and formal verification of IC designs.

Experience

10+ Years

Level

Senior

Education

Bachelor's in EE

Description :

1. Worked in cross-functional teams with architects, system engineers, verification engineers, layout designers, and manufacturing engineers. 
2. Stayed updated with industry advancements, new technologies, tools, methodologies, and best practices in IC design and semiconductor industry trends.
3. Skilled with EDA tools such as Cadence Virtuoso, Synopsys Design Compiler, IC Compiler, ModelSim, and VCS.
4. Qualified in DFT architecture, Hirarchical Scan Design, Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis. 
5. Experience in Extensiv RTL experience including design, verification, synthesis and timing closure.
6. Skilled with board-level testing is desirable.
7. Trained in ASIC Design, front-end RTL coding, complex state machine design.

Experience

2-5 Years

Level

Junior

Education

Bachelor's in EE

Description :

1. Designed in SiGe BiCMOS and/or CMOS.
2. Skilled with Cadence Tools (schematic entry, simulation, layout), FPGA-based systems, Python scripting.
3. Expertised on transistor level Analog and digital logic IC design experience using CMOS, BiCMOS or SOI processes.
4. Designed experience with different digital interface including SPI, MIPI, I^2C.
5. Trained with digital design flow (VHDL coding, RTL synthesis, logic simulation, place and route).
6. Utilized IC design industry standard tools such as Cadence simulation, layout, LVS verification and parasitic extractions.
7. Skilled with C/C++ and Scripting languages (Perl/Tcl/Python).

Experience

2-5 Years

Level

Executive

Education

Bachelor's in EE

Description :

1. Developed and executed test plans, and works with verification and validation engineers to design test methodologies that ensure product quality.
2. Executed large group and customer presentations.
3. Qualified with synthesis, STA, DFT, and standard ASIC design tools/flows.
4. Experienced with industry standard schematic entry and circuit simulation tools.
5. Experienced with IC design methodologies, RTL coding (VHDL/Verilog), synthesis, and physical design implementation.
6. Worked effectively in a cross-functional engineering environment.
7. Developed customization scripts for local optimization.

Experience

2-5 Years

Level

Executive

Education

Bachelor's in EE