Description :

1. Performed Audit Checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing Analysis, CTS and Detail Routing.
2. Analyzed Clock slews and skews and optimizing the clock tree for maintaining the slew and skew limits.
3. Analyzed Timing for blocks and fixed the timing violations.
4. Analyzed Timing violations that are due to Assertions issue and communicating with the timing engineer to solve the issue.
5. Used the concept of useful skew to fix timing violations for critical blocks.
6. Fixed DRCs, LVS and Electro Migration checks.
7. Generated multiple programs to parse, gather and analyze large volumes of complex multi-scenario timing data from apr block flows.

Experience

2-5 Years

Level

Executive

Education

Master Of Science

Description :

1. Designed and developed of Low Power SOC chips used in Cellular and Handheld applications.
2. Performed Physical Integration of large blocks ranging from 1M to 3M instances.
3. Designed and developed blocks from RTL to GDSII using a timing closure flow.
4. Tasks included floorplanning of single and multiple power domain designs, place and route, CTS, sign-off physical verification (DRC/LVS/ERC/ANTENNA).
5. Implemented STA ECOs for timing closure.
6. Evaluated and benchmarked study for area/timing/routability impact using 7 and 9 tracks library at 28nm process node.
7. Study was concluded with 15-20% improvement in frequency, about 18% area savings for standard cells and about 11% overall area savings for 7T compare to 9T.

Experience

7-10 Years

Level

Management

Education

MS In Electrical Engineering

Description :

1. Debugged using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full chip assembly, packaging, and verification.
2. Troubleshoot a wide variety up to and including difficult design issues and applied proactive intervention.
3. Scheduled, staff, executed and verifies complex chips development and execution of project methodologies and/or flow developments.
4. Generated block/chip level static timing constraints.
5. Built full chip floor-plan including pin placement, partitions and power grid. 
6. Developed and validated high performance low power clock network guidelines.
7. Performed block level place and route and close the design to meet timing, area and power constraints. 

Experience

7-10 Years

Level

Management

Education

MS In Electrical Engineering

Description :

1. Worked as the Physical Design Team leader for AMD's K5 Tape out team.
2. Responsible for all aspects of Layout, Layout verification, Tape out.
3. Required full coordination between all the Block owners to ensure that each block met all the design rules.
4. Responsible for training the newhires.
5. Generated sub-micron CMOS Circuit Layout from Schematics.
6. Floorplanned a major Block of AMD's K5 including sub blocks.
7. Wrote Ample and C shell Scripts to implement specific functions.

Experience

5-7 Years

Level

Junior

Education

Master Of Science In Electrical Engineering

Description :

1. Developed and implemented full lifecycle SoC/IP integration methodology, by performing and documenting chip synthesis, floor planning, clock tree insertion, and timing optimization utilizing Cadence SoC Encounter and Synopsys Astro/ICC tool suite.
2. Handled global and detail routing and final verification, including signal integrity issue prevention and verification, power analysis and management, LVS and DRC verification.
3. Played key role in successful on completion of over 10 SoC designs, all delivered on schedule.
4. Managed and trained design engineers in usage of Cadence and Synopsys SoC flow, resulting in reduced time for six sigma production parts.
5. Implemented TCL scripts to reproduce design flow, reducing SoC build time by 50% Comprehensively analyzed 65nm market and related competitive factors; modified processes for multiple products leading to reduced design time.
6. Extended existing clock tree capabilities to minimize skew and reduce insertion delays by programmatic routing techniques, H-trees, and OCV immunity buffer selection; succeeded in reducing required timing margin.
7. Developed customizable standard cell blocks on select products to enable customer personalization, while reducing non recurring custom costs.

Experience

10+ Years

Level

Senior

Education

MS

Description :

1. Partnered with process engineers to create new FET design layouts on next generation technology, and maintained legacy production designs for the Texas Instruments Lehigh Valley location Design forward-looking FET technology with multiple layout variations for next generation.
2. Designs assembled for test shuttles, which are used to help develop optimum performance die.
3. Coordinated work flow to the Dallas design teams, and provided design data that is used to floorplan photomask reticle layouts, that meet the wafer fab requirements.
4. Coordinated design work with wafer fabs across TI.
5. Maintained version controlled Design Sync Cadence data, which is shared across the entire TILV design team and teams across TI at multiple locations.
6. Maintained working libraries of documentation to meet TI requirements of device traceability.
7. Scheduled formal design review meetings, to gain team approval for device release to manufacturing.

Experience

5-7 Years

Level

Executive

Education

Bachelors

Description :

1. Experienced in debugging LVS, fixing DRC, fixing crosstalk, fixing IR, IVD and timing.
2. Expertised with complex custom pre-routing nets using Synopsys ICC compiler.
3. Expertised with metal repin only.
4. Drived floorplan layout reviews with design team and recommending changes due to congestion, DRC violation, IR and IVD.
5. Experienced with floor-planning, flat as well as hierarchical top-down flows.
6. Experienced with flip chip cover cell creation and power and signal trace route.
7. Experienced with 2.5D interposer design.

Experience

2-5 Years

Level

Executive

Education

MS

Description :

1. Had worked for the Client Nokia Siemens Networks (Finland) and Texas Instruments (Germany).
2. Intended for the Product Flexi Multiradio Base Station (FRM3.0).
3. Developed flows for topographical Synthesis, bottom-up approach in synthesizing the Top-Level.
4. Fixed the Timing violations in the designs pre-layout by tightening the constraints and tweaking the options of the Design compiler for a better optimization.
5. Worked closely with the designers in understanding the spec and developing the constraints for Synthesis.
6. Updated the Synthesis flow for a couple of Sub-chips so as to enable the Hierarchical floor-planning by the Customer.
7. Worked closely with the designers in fixing the LEC issues.

Experience

7-10 Years

Level

Management

Education

MS

Description :

1. Responsible for bus routing, pin optimization, and congestion analysis at the partition hierarchy using in-house tools and Synopsys ICC.
2. Automated Power distribution and maintained the power grid for the entire chip used by every partition integrator in the team.
3. Responsible for Hard Macro integration methodology; worked with DA and Library team to define layout parameters so that the IPs are DRC clean by construction; has good understanding of VLSI design flow and experience in DRC/LVS and DFM requirements in the various process technologies.
4. Co-defined, co-developed and tested verification flows critical for Full Chip tape-in quality clean up using Synopsys Hercules including hierarchical Layout vs.
5. Schematic Verification (LVS), Design Rule Checks (DRC), Reliability Verification (RV).
6. Experienced in both analog and digital layout designs; worked in all level of hierarchy from standard cells layout to top level assembly using PnR for PLLs and uROM macros.
7. Experienced in TCL and Perl programming languages.

Experience

10+ Years

Level

Senior

Education

M.S. In Electrical Engineering

Description :

1. Created synthesis and apr flow metric gathering tool suite to store block related metrics in MySQL database.
2. Performed block level synthesis and place and route of major design blocks.
3. Interfaced regularly with logic design.
4. Utilized Synopsys Design Compiler and IC Compiler knowledge to incorporate flow modifications.
5. Recently focused on flow metric gathering.
6. Wrote server side cgi web framework to visualize synthesis and apr flow metrics.
7. Produced object oriented TCL and C code tool framework that allow end users to quickly create complete and complex tool flows.

Experience

7-10 Years

Level

Management

Education

MS